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general description the max807 microprocessor (p) supervisory circuit reduces the complexity and number of components needed to monitor power-supply and battery-control func- tions in ? systems. a 70? supply current makes the max807 ideal for use in portable equipment, while a 2ns chip-enable propagation delay and 250ma output current capability (20ma in battery-backup mode) make it suit- able for larger, higher-performance equipment. the max807 comes in 16-pin dip, so, and tssop pack- ages, and provides the following functions: p reset. the active-low reset output is asserted dur- ing power-up, power-down, and brownout conditions, and is guaranteed to be in the correct state for v cc down to 1v. active-high reset output. manual-reset input. two-stage power-fail warning. a separate low-line comparator compares v cc to a threshold 52mv above the reset threshold. this low-line comparator is more accurate than those in previous ? supervisors. backup-battery switchover for cmos ram, real-time clocks, ?s, or other low-power logic. write protection of cmos ram or eeprom. 2.275v threshold detector provides for power-fail warning and low-battery detection, or monitors a power supply other than +5v. batt ok status flag indicates that the backup-battery voltage is above +2.275v. watchdog-fault output?sserted if the watchdog input has not been toggled within a preset timeout period. applications computers controllers intelligent instruments critical ? power monitoring portable/battery-powered equipment features ? precision 4.675v (max807l), 4.425v (max807m), or 4.575v (max807n) voltage monitoring ? 200ms power-ok/reset time delay ? reset and reset outputs ? independent watchdog timer ? 1a standby current ? power switching 250ma in v cc mode 20ma in battery-backup mode ? on-board gating of chip-enable signals; 2ns ce gate propagation delay ? maxcap and supercap compatible ? voltage monitor for power fail ? backup-battery monitor ? guaranteed reset valid to v cc = 1v ? 1.5% low-line threshold accuracy 52mv above reset threshold max807l/m/n full-featured p supervisory circuit with 1.5% reset accuracy ________________________________________________________________ maxim integrated products 1 19-0433; rev 4; 11/05 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 reset reset wdo ce in gnd v cc out batt top view max807 ce out wdi low line mr batt ok pfi pfo batt on dip/so/tssop pin configuration ordering information and typical operating circuit appear at end of data sheet. supercap is a registered trademark of baknor industries. maxcap is a registered trademark of cesiwid, inc.
max807l/m/n full-featured p supervisory circuit with 1.5% reset accuracy 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v cc = 4.60v to 5.5v for the max807l, v cc = 4.50v to 5.5v for the max807n, v cc = 4.35v to 5.5v for the max807m, v batt = 2.8v, v pfi = 0v, t a = t min to t max . typical values are tested with v cc = 5v and t a = +25?, unless otherwise noted.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. input voltages (with respect to gnd) v cc ..........................................................................-0.3v to 6v v batt .......................................................................-0.3v to 6v all other inputs......................................-0.3v to (v out + 0.3v) input current v cc peak ...........................................................................1.0a v cc continuous .............................................................500ma i batt peak......................................................................250ma i batt continuous .............................................................50ma gnd .................................................................................50ma all other inputs ................................................................50ma continuous power dissipation (t a = +70?) plastic dip (derate 10.53mw/? above +70?) ..........842mw wide so (derate 9.52mw/? above +70?)................762mw cerdip (derate 10.00mw/? above +70?) ...............800mw tssop (derate 6.70 mw/? above +70?) .................533mw operating temperature ranges max807_c_e ......................................................0? to +70? max807_e_e ...................................................-40? to +85? max807_mje ................................................-55? to +125? storage temperature range .............................-65? to +160? lead temperature (soldering, 10s) .................................+300? v batt = 2.8v, v cc = 3.0v v cc = 0v, v batt = 2.8v v cc = 3v, i out = 100ma v cc = 4.5v, i out = 250ma v batt = 2.0v, i out = 5ma, v cc = 0v v batt = 2.8v, i out = 10ma, v cc = 0v v batt = 4.5v, i out = 20ma, v cc = 0v conditions ? -1.0 1.0 batt standby current (note 3) -0.1 0.1 ? 50 supply current in battery- backup mode (excludes i out ) (note 2) 5 0.4 1 ? 70 110 supply current in normal operating mode (excludes i out ) v v batt - 0.20 v batt - 0.08 v out in battery-backup mode v batt - 0.25 v batt - 0.12 v batt - 0.17 ? 1.2 2.5 v cc to out on-resistance 1.8 1.0 1.4 units min typ max symbol parameter v 0 5.5 operating voltage range v batt , v cc (note 1) max807c/e max807m v batt = 2.0v, i out = 5ma v batt = 2.8v, i out = 10ma v batt = 4.5v, i out = 20ma ? 16 40 batt to out on-resistance 12 25 8.5 t a = +25? max807c/e max807m t a = +25? t a = t min to t max v batt = 2.8v power up power down v v batt battery-switchover threshold v batt + 0.05 v cc = 3v, v batt = 2.8v, i out = 100ma v cc = 4.5v v cc - 0.02 i out = 25ma i out = 250ma, max807c/e i out = 250ma, max807m v out in normal operating mode v v cc - 0.25 v cc - 0.12 v cc - 0.35 v cc - 0.22 v cc - 0.45 mv 0.1 0.4 battery-switchover hysteresis 50 batt on output, low voltage v rst (max) , i sink = 3.2ma v 2 2.7 batt on output, high voltage v cc = 0v, i source = 0.1ma, v batt = 2.8v v
max807l/m/n full-featured p supervisory circuit with 1.5% reset accuracy _______________________________________________________________________________________ 3 v ih electrical characteristics (continued) (v cc = 4.60v to 5.5v for the max807l, v cc = 4.50v to 5.5v for the max807n, v cc = 4.35v to 5.5v for the max807m, v batt = 2.8v, v pfi = 0v, t a = t min to t max . typical values are tested with v cc = 5v and t a = +25?, unless otherwise noted.) conditions units min typ max symbol parameter sink current 70 4.600 4.675 4.750 v 5 batt on output short-circuit current source current, v cc = 0v, v batt = 2.8v 4.350 4.425 4.500 low line to reset threshold voltage v lr reset threshold hysteresis v cc falling 30 52 70 mv 13 mv 4.500 4.575 4.650 v rst reset threshold v cc rising and falling 4.63 4.71 max807n v cc to low line delay v cc falling at 1mv/? 24 ? ? 26 v cc to reset delay v cc falling at 1mv/? 4.48 4.56 max807m minimum watchdog input pulse width watchdog-timeout period v il = 0.8v, v ih = 0.75 x v cc t wd 100 ns v 1.12 1.6 2.24 s ms 140 200 280 t rp reset active-timeout period v cc rising 4.73 4.81 max807l max807l max807n max807m 0.3 0.3 i sink = 50?, v batt = 0v, v cc falling v cc - 1.5 v cc - 0.1 reset output voltage i source = 0.1ma 0.1 0.4 i sink = 3.2ma, v cc = 4.25v ma 60 output sink current, v cc = 4.25v 1.6 i sc reset output short-circuit current output source current v cc = 1v, max807_c v cc = 1.2v, max807_e/m v 0.4 i sink = 3.2ma v cc - 1.5 reset output voltage i source = 5ma v 0.4 i sink = 3.2ma, v cc = 4.25v v cc - 1.5 low line output voltage i source = 5ma ma 60 output sink current 15 i sc reset output short-circuit current output source current, v cc = 4.25v ma 28 output sink current, v cc = 4.25v 20 i sc low line output short-circuit current output source current v 0.4 i sink = 3.2ma v cc - 1.5 wdo output voltage i source = 5ma ma ma 35 output sink current 20 i sc wdo output short-circuit current output source current v ll v low line threshold, v cc rising v 0.75 x v cc 0.8 v ih wdi threshold voltage (note 4) v il ? -50 -10 reset deasserted, wdi = 0v 16 50 wdi input current reset deasserted, wdi = v cc reset, low line, and watchdog timer
max807l/m/n full-featured p supervisory circuit with 1.5% reset accuracy 4 _______________________________________________________________________________________ note 1: either v cc or v batt can go to 0 if the other is greater than 2.0v. note 2: the supply current drawn by the max807 from the battery (excluding i out ) typically goes to 15? when (v batt - 0.1v) < v cc < v batt . in most applications, this is a brief period as v cc falls through this region (see typical operating characteristics ). note 3: ?? battery discharging current, ?? battery charging current. note 4: wdi is internally connected to a voltage-divider between v cc and gnd. if unconnected, wdi is driven to 1.8v (typical), disabling the watchdog function. note 5: overdrive (v od ) is measured from center of hysteresis band. note 6: the chip-enable resistance is tested with v ce in = v cc /2, and i ce in = 1ma. note 7: the chip-enable propagation delay is measured from the 50% point at ce in to the 50% point at ce out. electrical characteristics (continued) (v cc = 4.60v to 5.5v for the max807l, v cc = 4.50v to 5.5v for the max807n, v cc = 4.35v to 5.5v for the max807m, v batt = 2.8v, v pfi = 0v, t a = t min to t max . typical values are tested with v cc = 5v and t a = +25?, unless otherwise noted.) conditions units min typ max symbol parameter pfi leakage current ?.005 ?0 na mv 20 pfi hysteresis ? ?.00002 ? ce in leakage current disabled mode, mr = 0v ? 14 pfi to pfo delay (note 5) pfi input threshold v pft v pfi falling 2.22 2.285 2.35 v 2.20 2.265 2.33 reset to ce out delay v cc falling 28 ? ? 75 150 ce in to ce out resistance (note 6) enabled mode, v cc = v rst (max) mr minimum pulse input 1 ? ns 170 mr-to-reset propagation delay ma 17 ce out short-circuit current (reset active) v cc = 5v, disabled mode, ce out = 0, mr = 0v ns 28 ce in to ce out propagation delay (note 7) v cc = 5v, c load = 50pf, 50 ? source impedance driver v 3.5 ce out output voltage high (reset active) disabled mode, mr = 0v mr threshold v ih 2.4 v batt ok threshold v bok 2.200 2.265 2.350 v batt ok hysteresis 20 mv output voltage (pfo, batt ok) v ol i sink = 3.2ma 0.4 v output short-circuit current i sc output sink current 35 ma v pfi rising v batt - 0.1 v batt v cc = 5v, i out = 2ma v cc = 0v, i out = 10? v il 0.8 v oh i source = 5ma v cc - 1.5 output source current 20 v od = 30mv, v pfi falling mr pullup current mr = 0v 50 100 200 ? chip-enable gating manual reset input batt ok comparator logic outputs
max807l/m/n full-featured p supervisory circuit with 1.5% reset accuracy _______________________________________________________________________________________ 5 __________________________________________typical operating characteristics (v cc = 5v, v batt = 2.8v, pfi = 0, no load, t a = +25?, unless otherwise noted.) 80 60 -60 -20 60 140 v cc supply current vs. temperature (normal operating mode) 64 76 max807-01 temperature (?) v cc supply current ( a) 20 100 -40 40 120 080 72 68 62 66 78 74 70 3.0 2.5 2.0 1.5 1.0 0.5 0 -60 -20 60 140 battery supply current vs. temperature (battery-backup mode) max807-02 temperature (?) battery supply current ( a) 20 100 -40 40 120 080 6 5 4 3 2 1 0 -60 -20 60 140 chip-enable propagation delay vs. temperature max807-03 temperature (?) propagation delay (ns) 20 100 -40 40 120 080 30 5 -60 -20 60 140 batt-to-out on-resistance vs. temperature 10 25 max807-04 temperature ( c) batt-to-out on-resistance ( ? ) 20 100 -40 40 120 080 20 15 v batt = 2.0v v batt = 2.8v v batt = 4.5v v cc = 0v i out = 10ma 4.70 4.65 4.60 4.55 4.50 4.45 4.40 -60 -20 60 140 reset threshold vs. temperature max807-07 temperature (?) reset threshold (v) 20 100 -40 40 120 080 max807l max807n max807m 1.6 1.5 1.4 1.3 1.2 1.1 1.0 0.9 0.8 0.7 -60 -20 60 140 v cc -to-out on-resistance vs. temperature max807-05 temperature (?) v cc -to-out on-resistance ( ? ) 20 100 -40 40 120 080 i out = 250ma 2.340 2.320 2.300 2.280 2.260 2.240 2.220 2.200 -60 -20 60 140 pfi threshold vs. temperature (v pfi falling) max807-06 temperature (?) pfi threshold (v) 20 100 -40 40 120 080 280 260 240 220 200 180 160 140 -60 -20 60 140 reset timeout period vs. temperature (v cc rising) max807-08 temperature (?) reset timeout period (ms) 20 100 -40 40 120 080 0 10 20 30 40 50 60 70 80 -60 -20 60 140 low line -to-reset threshold vs. temperature (v cc falling) max807-09 temperature (?) low line-to-reset threshold (mv) 20 100 -40 40 120 080
max807l/m/n full-featured p supervisory circuit with 1.5% reset accuracy 6 _______________________________________________________________________________________ t ypical operating characteristics (contiued) (v cc = 5v, v batt = 2.8v, pfi = 0, no load, t a = +25?, unless otherwise noted.) 4.75 4.80 4.70 4.65 4.60 4.55 4.50 4.45 4.40 -60 -20 60 140 low line threshold vs. temperature (v cc rising) max807-10 temperature (?) low line threshold (v) 20 100 -40 40 120 080 l version n version m version 0 5 10 15 20 25 30 35 40 -60 -20 60 140 low line comparator propagation delay vs. temperature (v cc falling) max807-11 temperature (?) low line comparator prop delay ( s) 20 100 -40 40 120 080 v cc falling at 1mv/ s 0 5 10 15 20 25 30 35 40 -60 -20 60 140 reset comparator propagation delay vs. temperature (v cc falling) max807-12 temperature (?) reset comparator prop delay ( s) 20 100 -40 40 120 080 v cc falling at 1mv/ s 0 2 4 6 8 10 12 14 16 2.5 2.6 2.7 2.8 2.9 3.0 battery current vs. input supply voltage max807-13 v cc (v) battery current ( a) 1000 100 10 1 1 100 10 1000 v cc -to-out vs. output current max807-16 i out (ma) v cc - vout (mv) slope = 1.0 ? 0 50 ? driver 2 4 6 8 050 100 chip-enable propagation delay vs. ce out load capacitance max807-14 c load (pf) propagation delay (ns) 1000 100 10 110100 batt-to-out vs. output current max807-15 i out (ma) batt-to-out (mv) v cc = 0v slope = 12 ? 1000 100 10 1 1 100 10 1000 maximum transient duration vs. reset comparator overdrive max807-17 reset comparator overdrive (mv) maximum transient duration ( s) reset occurs
max807l/m/n full-featured p supervisory circuit with 1.5% reset accuracy _______________________________________________________________________________________ 7 pin description active-low reset output. reset is triggered and stays low when v cc is below the reset threshold or when mr is low. it remains low 200ms after v cc rises above the reset threshold or mr returns high. reset has a strong pulldown but a relatively weak pullup, and can be wire-or connected to logic gates. valid for v cc 1v. reset swings between v cc and gnd. reset 9 watchdog output. this cmos-logic output goes low if wdi remains high or low longer than the watch- dog-timeout period (t wd ), and remains low until the next transition of wdi. wdo remains high if wdi is unconnected. wdo is high during reset. wdo swings between v cc and gnd. connect wdo to mr to generate resets during watchdog faults. wdo 10 chip-enable output. output to the chip-enable gating circuit. ce out is pulled up to the higher of v cc or v batt , when the chip-enable gate is disabled. ce out 11 chip-enable input ce in 12 battery-on output. cmos-logic output/external bypass switch driver. high when out is connected to batt and low when out is connected to v cc . connect the base of a pnp transistor or gate of a pmos transistor to batt on for i out requirements exceeding 250ma. batt on swings between the higher of v cc and v batt and gnd. batt on 13 ground gnd 5 manual-reset input. a logic low on mr asserts reset. reset remains asserted as long as mr remains low and for 200ms after mr returns high. mr is an active-low input with an internal pullup to v cc . it can be driven using ttl or cmos logic, or shorted to ground with a switch. connect to v cc , or leave uncon- nected if not used. mr 6 low-line comparator output. this cmos-logic output goes low when v cc falls to 52mv above the reset threshold. use this output to generate an nmi to initiate an orderly shutdown routine when v cc is falling. low line swings between v cc and gnd. low line 7 active-high reset output. reset is the inverse of reset. it is a cmos output that sources and sinks current. reset swings between v cc and gnd. reset 8 watchdog input. if wdi remains high or low longer than the watchdog-timeout period (1.6s, typ), wdo goes low. leave unconnected to disable the watchdog function. wdi 4 input supply voltage, nominally +5v. bypass with a 0.1? capacitor to gnd. v cc 3 pin power-fail output. this cmos-logic output goes low when pfi is less than v pft (2.265v). valid for v cc 4v. pfo swings between v cc and gnd. pfo 2 power-fail input. when pfi is less than v pft (2.265v), pfo goes low. connect to ground when unused. pfi 1 function name backup-battery input. when v cc falls below the reset threshold and v batt , out switches from v cc to batt. v batt may exceed v cc . the battery can be removed while the max807 is powered-up, provided batt is bypassed with a 0.1? capacitor to gnd. if no battery is used, connect batt to ground, and connect v cc and out together. batt 14 battery-ok signal output. high in normal operating mode when v batt exceeds v bok (2.265v). valid for v cc 4v. batt ok 15 output supply voltage to cmos ram. when v cc exceeds the reset threshold or v cc > v batt , out is connected to v cc . when v cc falls below the reset threshold and v batt , out connects to batt. bypass out with a 0.1? capacitor to gnd. out 16
detailed description the max807 ? supervisory circuit provides power- supply monitoring, backup-battery switchover, and pro- gram execution watchdog functions in ? systems (figure 1). use of bicmos technology results in an improved 1.5% reset-threshold precision, while keeping supply currents typically below 70?. the max807 is intended for battery-powered applications that require high reset-threshold precision, allowing a wide power- supply operating range while preventing the system from operating below its specified voltage range. reset and reset outputs the max807? reset output ensures that the ? pow- ers up in a known state, and prevents code execution errors during power-down and brownout conditions. it accomplishes this by resetting the ?, terminating pro- gram execution when v cc dips below the reset thresh- old or mr is pulled low. each time reset is asserted it stays low for the 200ms reset timeout period, which is set by an internal timer to ensure the ? has adequate time to return to an initial state. any time v cc goes below the reset threshold before the reset-timeout peri- od is completed, the internal timer restarts. the watch- dog timer can also initiate a reset if wdo is connected to mr (see the watchdog input section). max807l/m/n full-featured p supervisory circuit with 1.5% reset accuracy 8 _______________________________________________________________________________________ max807 ce in pfi gnd v cc batt v cc the higher of v cc or v batt battery-backup comparator reset comparator low-line comparator battery-ok comparator power-fail comparator 2.275v p out batt on low line batt ok pfo wdi mr 50k ? reset reset wdo ce out n p p n watchdog transition detector state machine oscillator figure 1. block diagram
max807l/m/n full-featured p supervisory circuit with 1.5% reset accuracy _______________________________________________________________________________________ 9 the reset output is active low and implemented with a strong pulldown/relatively weak pullup structure. it is guaranteed to be a logic low for 0 < v cc < v rst , pro- vided v batt is greater than 2v. without a backup bat- tery, reset is guaranteed valid for v cc 1. it typically sinks 3.2ma at 0.1v saturation voltage in its active state. the reset output is the inverse of the reset output; it both sources and sinks current and cannot be wire-or connected. figure 2a shows a timing diagram with v cc rising and figure 2b shows v cc falling. manual reset input many ?-based products require manual-reset capabil- ity to allow an operator or test technician to initiate a reset. the manual reset (mr) input permits the genera- tion of a reset in response to a logic low from a switch, wdo, or external circuitry. reset remains asserted while mr is low, and for 200ms after mr returns high. mr has an internal 50? to 200? pullup current, so it can be left open if it is not used. mr can be driven with ttl or cmos-logic levels, or with open-drain/collector outputs. connect a normally open momentary switch from mr to gnd to create a manual-reset function; external debounce circuitry is not required. if mr is dri- ven from long cables or if the device is used in a noisy environment, connect a 0.1? capacitor from mr to ground to provide additional noise immunity. as shown in figure 3, diode-ored connections can be used to allow manual resets from multiple sources. figure 4 shows the reset timing. watchdog timer watchdog input the watchdog circuit monitors the ?? activity. if the ? does not toggle the watchdog input (wdi) within 1.6s, wdo goes low. the internal 1.6s timer is cleared and wdo returns high when reset is asserted or when a transition (low-to-high or high-to-low) occurs at wdi while reset is high. as long as reset is asserted, the timer remains cleared and does not count. as soon as reset is released, the timer starts counting (figure 5). supply current is typically reduced by 10? when wdi is at a valid logic level. v reset v low line v cc (max801) v reset (max808) v ce out v rst v ll t rp t rp v batt shown for v cc = 0 to 5v, v batt = 2.8v, ce in = gnd v reset v low line v cc v reset v ce out v rst v rst + v lr v batt shown for v cc = 5v to 0, v batt = 2.8v, ce in = gnd figure 2a. timing diagram, v cc rising figure 2b. timing diagram, v cc falling max807 * * other reset sources manual reset mr *diodes not required on open-drain outputs. figure 3. diode ?r?connections allow multiple reset sources to connect to mr
max807l/m/n full-featured p supervisory circuit with 1.5% reset accuracy 10 ______________________________________________________________________________________ watchdog output wdo remains high if there is a transition or pulse at wdi during the watchdog-timeout period. wdo goes low if no transition occurs at wdi during the watchdog- timeout period. the watchdog function is disabled and wdo is a logic high when v cc is below the reset threshold or wdi is an open circuit. to generate a sys- tem reset on every watchdog fault, diode-or connect wdo to mr (figure 6). when a watchdog fault occurs in this mode, wdo goes low, which pulls mr low, caus- ing a reset pulse to be issued. as soon as reset is asserted, the watchdog timer clears and wdo returns high. with wdo connected to mr, a continuous high or low on wdi will cause 200ms reset pulses to be issued every 1.6s. chip-enable signal gating the max807 provides internal gating of chip-enable (ce) signals to prevent erroneous data from corrupting the cmos ram in the event of a power failure. during normal operation, the ce gate is enabled and passes all ce transitions. when reset is asserted, this path becomes disabled, preventing erroneous data from corrupting the cmos ram. the max807 uses a series transmission gate from the chip-enable input (ce in) to the chip-enable output (ce out) (figure 1). the 8ns (max) chip-enable propagation from ce in to ce out enables the max807 to be used with most ?s. chip-enable input ce in is high impedance (disabled mode) while reset is asserted. during a power-down sequence when v cc passes the reset threshold, the ce transmission gate disables and ce in becomes high impedance 28? after reset is asserted (figure 7). during a power-up sequence, ce in remains high impedance (regardless of ce in activity) until reset is deasserted following the reset-timeout period. in the high-impedance mode, the leakage currents into this input are ?? (max) over temperature. in the low- impedance mode, the impedance of ce in appears as a 75 ? resistor in series with the load at ce out. the propagation delay through the ce transmission gate depends on both the source impedance of the drive to ce in and the capacitive loading on ce out mr reset ce in 0v 170ns 28 s typ 1 s min ce out v cc v rst reset t wd wdo wdi wdo connected to p interrupt. t rp figure 4. manual-reset timing diagram figure 5. watchdog timing relationship v cc v cc reset wdo wdo 4.7k ? to p mr reset wdi t rp t rp t wd 50 s max807 figure 6. generating a reset on each watchdog fault
max807l/m/n full-featured p supervisory circuit with 1.5% reset accuracy ______________________________________________________________________________________ 11 (see the chip-enable propagation delay vs. ce out load capacitance graph in the typical operating characteristics ). the ce propagation delay is produc- tion tested from the 50% point on ce in to the 50% point on ce out using a 50 ? driver and 50pf of load capacitance (figure 8). for minimum propagation delay, minimize the capacitive load at ce out and use a low output-impedance driver. chip-enable output in the enabled mode, the impedance of ce out is equiv- alent to 75 ? in series with the source driving ce in. in the disabled mode, the 75 ? transmission gate is off and ce out is actively pulled to the higher of v cc or v batt . this source turns off when the transmission gate is enabled. low-line comparator the low-line comparator monitors v cc with a threshold voltage typically 52mv above the reset threshold, with 13mv of hysteresis. use low line to provide a non- maskable interrupt (nmi) to the ? when power begins to fall to initiate an orderly software shutdown routine. in most battery-operated portable systems, reserve energy in the battery provides ample time to complete the shutdown routine once the low-line warning is encountered, and before reset asserts. if the system must contend with a more rapid v cc fall time?uch as when the main battery is disconnected, a dc-dc converter shuts down, or a high-side switch is opened during normal operation?se capacitance on the v cc line to provide time to execute the shutdown routine (figure 9). first calculate the worst-case time required for the system to perform its shutdown routine. then, with the worst-case shutdown time, the worst-case load current, and the minimum low-line to reset threshold (v lr(min) ), calculate the amount of capacitance required to allow the shutdown routine to complete before reset is asserted: c hold = (i load x t shdn ) / v lr (min) where t shdn is the time required for the system to com- plete the shutdown routine, and includes the v cc to low-line propagation delay; and where i load is the cur- rent being drained from the capacitor, v lr is the low- line to reset threshold. v cc ce in reset threshold ce out reset reset 26 s 28 s 26 s max807 ce in 50pf c load ce out gnd v rst max 50 ? driver v cc figure 7. reset and chip-enable timing figure 8. ce propagation delay test circuit gnd v cc to p nmi c hold c hold > i load x t shdn v lr 4.5v to 5.5v low line max807 regulator figure 9. using low line to provide a power-fail warning to the ?
max807l/m/n power-fail comparator pfi is the noninverting input to an uncommitted com- parator. if pfi is less than v pft (2.265v), pfo goes low. the power-fail comparator is intended to monitor the preregulated input of the power supply, providing an early power-fail warning so software can conduct an orderly shutdown. it can also be used to monitor sup- plies other than 5v. set the power-fail threshold with a resistor-divider, as shown in figure 10. power-fail input pfi is the input to the power-fail comparator. the typical comparator delay is 14? from v il to v ol (power failing), and 32? from v ih to v oh (power being restored). if unused, connect this input to ground. power-fail output the power-fail output (pfo) goes low when pfi goes below v pft . it typically sinks 3.2ma with a saturation voltage of 0.1v. with pfi above v pft , pfo is actively pulled to v cc . connecting pfi through a voltage- divider to a preregulated supply allows pfo to gener- ate an nmi as the preregulated power begins to fall (figure 11b). if the preregulated supply is inaccessible, use low line to generate the nmi (figure 11a). the low line threshold is typically 52mv above the reset threshold (see the low-line comparator section). full-featured p supervisory circuit with 1.5% reset accuracy 12 ______________________________________________________________________________________ max807 v cc gnd pfi pfo r1 r2 v in 0v v in pfo v trip v l v pft = 2.265v v pfh = 20mv where v trip = r2 + r1 1 ) ( r2 1 r1 v cc (v pft + v pfh ) v l = r2 + r1 1 ) ( r2 1 r1 v cc (v pft ) note: v trip, v l are negative. v cc max807 v cc gnd pfi pfo r1 r2 pfo v trip v h v in v trip = ) ( r2 r1 + r2 v pft v h = (v pft + v pfh ) v cc v in mr b) a) ) ( r2 r1 + r2 max807 out v cc from regulated supply power to cmos ram batt reset low line wdi gnd reset nmi i/o line p p power 0.1 f 0.1 f 2.8v a) b) max807 out v cc pfi power to cmos ram batt reset pfo wdi gnd voltage regulator reset nmi i/o line p p power 0.1 f 0.1 f 2.8v figure 10. using the power-fail comparator to monitor an additional power supply: a) v in is negative, b) v in is positive figure 11. a) if the preregulated supply is inaccessible, low line generates the nmi for the ?. b) use pfo to generate the ? nmi if the preregulated supply is accessible.
battery-backup mode battery backup preserves the contents of ram in the event of a brownout or power failure. with a backup battery installed at batt, the max807 automatically switches ram to backup power when v cc falls. two conditions are required for switchover to battery-back- up mode: 1) v cc must be below the reset threshold; 2) v cc must be below v batt . table 1 lists the status of inputs and outputs during battery-backup mode. backup-battery input the batt input is similar to v cc , except the pmos switch is much smaller. this input is designed to con- duct up to 20ma to out during battery backup. the on-resistance of the pmos switch is approximately 13 ? . figure 12 shows the two series pass elements between the batt input and out that facilitate ul approval. v batt can exceed v cc during normal opera- tion without causing a reset. output supply voltage the output supply (out) transfers power from v cc or batt to the ?, ram, and other external circuitry. at the maximum source current of 250ma, v out will typi- cally be 260mv below v cc . decouple this terminal with a 0.1? capacitor. batt on output t he battery on (batt on) output indicates the status of the internal battery switchover comparator, which con- trols the internal v cc and batt switches. for v cc greater than v batt (ignoring the small hysteresis effect), batt on typically sinks 3.2ma at 0.4v. in bat- tery-backup mode, this output sources approximately 5ma. use batt on to indicate battery switchover sta- tus, or to supply gate or base drive for an external pass transistor for higher current applications (see the typical operating circuit ). max807l/m/n full-featured p supervisory circuit with 1.5% reset accuracy ______________________________________________________________________________________ 13 figure 12. v cc and batt-to-out switch max807 p pp out v cc batt 0.1 f control circuitry table 1. input and output status in battery-backup mode the power-fail comparator remains active in battery-backup mode for v cc 4v. below 4v, pfo is forced low. pfo 2 wdi is ignored and goes high impedance wdi 4 battery switchover comparator monitors v cc for active switchover. v cc 3 mr is ignored mr 6 logic high; the open-circuit output voltage is equal to v cc . reset 8 logic low low line 7 ground?v reference for all signals gnd 5 logic high. the open-circuit output voltage is equal to v cc . wdo 10 high impedance ce in 12 logic high. the open-circuit output voltage is equal to v batt . ce out 11 supply current is 1? maximum for v batt 2.8v. batt 14 pin out is connected to batt through two internal pmos switches in series. out 16 the power-fail comparator remains active in battery-backup mode for v cc 4v. pfi 1 function name logic high when v batt exceeds 2.285v. valid for v cc 4v. below 4v, batt ok is forced low. batt ok 15 logic high. the open-circuit output voltage is equal to v batt . batt on 13 logic low reset 9
max807l/m/n batt ok output the batt ok comparator monitors the backup battery voltage, comparing it with a 2.265v reference (v cc 4v). batt ok remains high as long as the backup bat- tery voltage remains above 2.265v, signaling that the backup battery has sufficient voltage to maintain the memory of static ram. when the battery voltage drops below 2.265v, the batt ok output drops low, signaling that the backup battery needs to be changed. applications information the max807 is not short-circuit protected. shorting out to ground, other than power-up transients such as charging a decoupling capacitor, may destroy the device. if long leads connect to the ic? inputs, ensure that these lines are free from ringing and other condi- tions that would forward bias the ic? protection diodes. there are two distinct modes of operation: 1) normal operating mode, with all circuitry powered up. typical supply current from v cc is 70?, while only leakage currents flow from the battery. 2) battery-backup mode, where v cc is below v batt and v rst . the supply current from the battery is typ- ically less than 1?. using supercaps or maxcaps with the max807 batt has the same operating voltage range as v cc , and the battery-switchover threshold voltage is typically v batt when v cc is decreasing or v batt + 0.06v when v cc is increasing. this hysteresis allows use of a supercap (e.g., order of 0.47f) and a simple charging circuit as a backup source (figure 13). since v batt can exceed v cc while v cc is above the reset threshold, there are no special precautions when using these ? supervisors with a supercap. alternative chip-enable gating using memory devices with ce and ce inputs allows the max807 ce loop to be bypassed. to do this, con- nect ce in to ground, pull up ce out to out, and connect ce out to the ce input of each memory device (figure 14). the ce input of each part then con- nects directly to the chip-select logic, which does not have to be gated by the max807. adding hysteresis to the power-fail comparator the power-fail comparator has a typical input hystere- sis of 20mv. this is sufficient for most applications where a power-supply line is being monitored through an external voltage-divider (figure 10). figure 15 shows how to add hysteresis to the power-fail comparator. select the ratio of r1 and r2 such that pfi sees 2.265v when v in falls to the desired trip point (v trip ). resistor r3 adds hysteresis. it will typically be an order of magnitude greater than r1 or r2. the cur- rent through r1 and r2 should be at least 1? to ensure that the 25na (max) pfi input current does not shift the trip point. r3 should be larger than 10k ? to prevent it from loading down the pfo pin. capacitor c1 adds additional noise rejection. full-featured p supervisory circuit with 1.5% reset accuracy 14 ______________________________________________________________________________________ figure 13. supercap or maxcap on batt max807 0.47f 1n4148 +5v v cc gnd batt out figure 14. alternate ce gating max807 out gnd ce in ce ce ce out ce ce ce ce ce ce *maximum rp value depends on the number of rams. minimum rp value is 1k ?. active-high ce lines from logic ram 1 ram 2 ram 3 ram 4 rp*
backup-battery replacement the backup battery may be disconnected while v cc is above the reset threshold, provided batt is bypassed with a 0.1? capacitor to ground. no precautions are necessary to avoid spurious reset pulses. negative-going v cc transients while issuing resets to the ? during power-up, power- down, and brownout conditions, these supervisors are relatively immune to short-duration negative-going v cc transients (glitches). it is usually undesirable to reset the ? when v cc experiences only small glitches. the typical operating characteristics show maximum transient duration vs. reset comparator overdrive, for which reset pulses are not generated. the graph was produced using negative-going v cc pulses, starting at 5v and ending below the reset threshold by the magni- tude indicated (reset comparator overdrive). the graph shows the maximum pulse width that a negative-going v cc transient may typically have without causing a reset pulse to be issued. as the amplitude of the tran- sient increases (i.e., goes farther below the reset threshold), the maximum allowable pulse width decreases. typically, a v cc transient that goes 40mv below the reset threshold and lasts for 3? or less will not cause a reset pulse to be issued. a 0.1? bypass capacitor mounted close to the v cc pin provides additional transient immunity. watchdog software considerations to help the watchdog timer keep a closer watch on soft- ware execution, you can use the method of setting and resetting the watchdog input at different points in the program, rather than ?ulsing?the watchdog input high- low-high or low-high-low. this technique avoids a ?tuck loop where the watchdog timer continues to be reset within the loop, keeping the watchdog from timing out. figure 16 shows an example flow diagram where the i/o driving the watchdog input is set high at the begin- ning of the program, set low at the beginning of every subroutine or loop, then set high again when the pro- gram returns to the beginning. if the program should ?ang?in any subroutine, the i/o is continually set low and the watchdog timer is allowed to time out, causing a reset or interrupt to be issued. maximum v cc fall time the v cc fall time is limited by the propagation delay of the battery switchover comparator and should not exceed 0.03v/?. a standard rule for filter capacitance on most regulators is on the order of 100? per amp of current. when the power supply is shut off or the main battery is disconnected, the associated initial v cc fall rate is just the inverse or 1a / 100? = 0.01v/?. the v cc fall rate decreases with time as v cc falls exponen- tially, which more than satisfies the maximum fall-time requirement. max807l/m/n full-featured p supervisory circuit with 1.5% reset accuracy ______________________________________________________________________________________ 15 figure 15. adding hysteresis to the power-fail comparator max807 v cc gnd pfi *optional r2 r3 r1 v in +5v c1* to p pfo v trip = 2.265 r1 + r2 r2 v h = 2.265 / r2 || r3 v l - 2.265 + 5 - 2.265 = 2.265 r1 + r2 || r3 r1 r3 r2 pfo +5v 0v 0v v h v trip v in v l figure 16. watchdog flow diagram start set wdi low subroutine or program loop, set wdi high return end
maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 16 __________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 (408) 737-7600 2005 maxim integrated products printed usa is a registered trademark of maxim integrated products, inc. max807l/m/n full-featured p supervisory circuit with 1.5% reset accuracy max807 reset reset reset +12v supply failure batt ok pfo wdo low line wdi ce in ce out +5v +12v supply out batt real- time clock * maxcap. mr other system reset sources batt on address decode 0.1 f 0.1 f 0.47f* v cc pfi gnd p push- button switch cmos ram a0?15 i/o nmi reset interrupt watchdog failure t ypical operating circuit ___________________chip information 4.425 4.50 4.35 m 4.675 4.575 4.65 typ 4.75 reset threshold (v) 4.60 4.50 max min n l suffix 16 plastic dip -40? to +85? max807_epe 16 wide so 0? to +70? max807_cwe 16 cerdip 16 wide so 16 plastic dip pin-package temp range 0? to +70? -40? to +85? -55? to +125? max807_mje max807_ewe max807_cpe part ? transistor count: 984 ordering information ? this part offers a choice of reset threshold voltage. from the table below, select the suffix corresponding to the desired threshold and insert it into the blank to complete the part number. devices in pdip, so and tssop packages are available in both leaded and lead-free packaging. specify lead free by adding the + symbol at the end of the part number when ordering. lead free not available for cerdip package. 16 tssop 0? to +70? max807_cue 16 tssop -40? to +85? max807_eue

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